The present invention relates to an apparatus for, and a method of, detecting and displaying a critical path in order to support work for laying out cells and for timing closure in the development of large scale integrated circuits (LSI).
Work for laying out various cells on the chip and for timing closure is a large component in the development of an LSI. Efficiency in this work greatly affects the time needed for development. In general, work which is carried out until work for timing closure is performed in the following procedure.    1. A responsible engineer for logic architecture of an LSI prepares a netlist of the design.    2. An engineer responsible lays out macro cells, including an input/output (I/O) cell, a hard core, a static random access memory (SRAM), and a register array on the chip by means of manual operation on the basis of a floor plan of the entire chip.    3. A layout tool to be executed by a computer lays out other gates (basic cells), which are included in the aforementioned netlist, on the chip while pursuing optimization of timings and wiring.    4. The layout tool to be executed by the computer executes a timing job for design data obtained after the cells are placed, and outputs a timing report (end-point report or the like) of each path (signal-propagating path). The path is a route through which a signal propagates. The path started at a pin of a gate (usually a clock pin of a latch) which is termed as a start point, passes through some pins of gates halfway, and ends at a pin (a data pin of a usual latch) of a gate which is termed as an end point.    5. The engineer responsible for the layout refers to an output result of the fourth step. The engineer responsible for the layout thereby analyzes, and identifies, a cause of having a path (a critical path) through which a signal was unable to propagate in a provided timing (a signal was not propagated in time).    6. If the cause of the critical path is found in the floor plan by the analysis in the fifth step, the work returns to the third step, where the floor plan is modified. In a case where the cause is that the path is logically too deep, the work returns to the first step, where the netlist is altered. If it is found that a simple alteration can meet the timing constrains, the work proceeds to the ensuing process (descriptions is omitted).
The analysis of the critical path by the engineer responsible for the layout in the fifth step can be carried out by means of referring to end-point reports which have been made in the fourth step and an image obtained by overlaying the critical path with the chip which has been displayed on a display. This image can be created by means of detecting the critical path from the timing reports such as the end-point reports.
There have been techniques proposed by others of causing a computer to automatically execute a timing job as described in the fourth step to find a critical path as well as a technique of displaying a critical path in a visible manner. For example, the technique of finding a critical path is disclosed in Japanese Patent Laid-open Official Gazette No. Hei. 6-282597. In another example the technique of displaying a critical path is disclosed in Japanese Patent Laid-open Official Gazette No. Hei. 8-50608.
As described above, the technique of detecting, and visibly displaying, a critical path by use of a computer has been heretofore realized in order to analyze the critical path in the development of an LSI.
However, in a case where there are many critical paths (for example, hundreds of critical paths) in an initial stage or the like of the layout work, if the detected critical paths are displayed one by one, it requires a lot of time and labor to analyze the displayed critical paths.
On the other hand, if all of the detected critical paths are displayed at a time, the critical paths are so crowded on the display screen that it is difficult to identify each of the critical paths visibly.